Download E-books Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science) PDF

By Jeong-Taek Kong

Digital Timing Macromodeling for VLSI layout Verification firstly offers an in depth heritage of the advance of simulation concepts. It offers designated dialogue of some of the ideas applied in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It additionally discusses mixed-mode simulation and interconnection research tools. The assessment in bankruptcy 2 offers an knowing of the benefits and negative aspects of the various concepts utilized in smooth electronic macromodels.
The booklet additionally offers a large choice of suggestions for acting nonlinear macromodeling of electronic MOS subcircuits which handle a huge variety of shortcomings in present electronic MOS macromodels. in particular, the options deal with the equipment version aspect, transistor coupling capacitance, powerful channel size modulation, sequence transistor relief, potent transconductance, enter terminal dependence, gate parasitic capacitance, the physique impression, the effect of parasitic RC-interconnects, and the impact of transmission gates. The concepts deal with significant resources of mistakes in present macromodeling recommendations, which needs to be addressed if macromodeling is to be accredited in advertisement CAD instruments by way of chip designers. The innovations awarded in Chapters 4-6 should be carried out in different macromodels, and are established utilizing the macromodel awarded in bankruptcy three. the recent strategies are proven over a really broad diversity of working stipulations: a lot wider than has been offered for earlier macromodels, therefore demonstrating the big variety of applicability of those strategies.

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