Formal Equivalence Checking and layout Debugging covers significant themes in layout verification: good judgment equivalence checking and layout debugging. the 1st a part of the ebook experiences the layout difficulties that require common sense equivalence checking and describes the underlying applied sciences which are used to resolve them. a few novel ways to the issues of verifying layout revisions after extensive sequential alterations equivalent to retiming are defined in aspect.
the second one a part of the booklet provides an intensive survey of past and contemporary literature on layout errors prognosis and layout blunders correction. This half additionally offers an in-depth research of the algorithms utilized in good judgment debugging software program courses, ErrorTracer and AutoFix, constructed through the authors.
From the Foreword:
`With the adoption of the static sign-off method of verifying circuit implementations the application-specific built-in circuit (ASIC) will adventure the 1st radical methodological revolution because the adoption of common sense synthesis. Equivalence checking is without doubt one of the serious components of this methodological revolution. This ebook is well timed for both the dressmaker trying to larger comprehend the mechanics of equivalence checking or for the CAD researcher who needs to enquire well-motivated study difficulties equivalent to equivalence checking of retimed designs or blunders analysis in sequential circuits.'
Kurt Keutzer, collage of California, Berkeley
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