Bankruptcy 6 Architecting Testbenches 221 Reusable Verification parts 221 Procedural Interface 225 improvement method 226 Verilog Implementation 227 Packaging Bus-Functional types 228 application applications 231 VHDL Implementation 237 Packaging Bus-Functional strategies 238 240 making a attempt Harness 243 Abstracting the Client/Server Protocol dealing with keep watch over signs 246 a number of Server cases 247 application programs 249 independent iteration and tracking 250 self sufficient Stimulus 250 Random Stimulus 253 Injecting mistakes 255 independent tracking 255 258 independent errors Detection enter and Output Paths 258 Programmable Testbenches 259 Configuration documents 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 best point Generics and Parameters 266 precis 268 bankruptcy 7 Simulation administration 269 Behavioral versions 269 Behavioral as opposed to Synthesizable versions 270 instance of Behavioral Modeling 271 features of a Behavioral version 273 x Writing Testbenches: useful Verification of HDL types Modeling Reset 276 Writing stable Behavioral types 281 Behavioral versions Are quicker 285 the price of Behavioral versions 286 some great benefits of Behavioral types 286 Demonstrating Equivalence 289 cross or Fail? 289 dealing with Simulations 292 294 Configuration administration Verilog Configuration administration 295 VHDL Configuration administration 301 SDF Back-Annotation 305 Output dossier administration 309 Regression 312 working Regressions 313 Regression administration 314 precis 316 APPENDIX A Coding directions 317 listing constitution 318 VHDL particular 320 Verilog particular 320 normal Coding instructions 321 reviews 321 format 323 Syntax 326 Debugging 329 Naming instructions 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL particular Filenames 336 HDL Coding directions 336 337 constitution 337 structure